NES CPU
From NESdevWiki
The NES CPU core is based on the 6502 processor and runs at approximately 1.79 MHz (1.66 MHz in a PAL NES). It is made by Ricoh and lacks the MOS6502's decimal mode.
In the NTSC NES, the RP2A03 chip contains the CPU and APU; in the PAL NES, the CPU and APU are contained within the RP2A07 chip.
See Power-Up State for the register values on power-up and after a reset. The CPU's clock is obtained by dividing a 21.477272 MHz clock source by 12 (26.601712 MHz divided by 16 for PAL).
The official 6502 Manual covers most details. 6502.org has lots of useful information and a discussion board.
Contents |
[edit] CPU Pinout and Signal Description
| AD1 - 01 | 40 - +5V |
| AD2 - 02 | 39 - STR |
| /RST - 03 | 38 - E44 |
| A00 - 04 | 37 - E45 |
| A01 - 05 | 36 - /OE1 |
| A02 - 06 | 35 - /OE2 |
| A03 - 07 | 34 - R/W |
| A04 - 08 | 33 - NMI |
| A05 - 09 | 32 - /IRQ |
| A06 - 10 | 31 - M2 |
| A07 - 11 | 30 - GND |
| A08 - 12 | 29 - CLK |
| A09 - 13 | 28 - D0 |
| A10 - 14 | 27 - D1 |
| A11 - 15 | 26 - D2 |
| A12 - 16 | 25 - D3 |
| A13 - 17 | 24 - D4 |
| A14 - 18 | 23 - D5 |
| A15 - 19 | 22 - D6 |
| GND - 20 | 21 - D7 |
Active-Low signals are indicated by a "/".
- -- CLK is of course the 21.47727 MHz clock input. Internally, the real clock is derived by dividing the input clock frequency by 12.
- -- AD1 and AD2 are the Audio Out pins.
- -- Axx is the address bus and Dx the data bus.
- -- STR stands for "strobe" and goes to the controller ports,
- -- /OE1 and /OE2 also go to the controller ports, and enables the output of it's respective controller, if present.
- -- E44 and E45 goes to expansion port pin 44 and 45, respectively.
- -- R/W is the read/write signal, which is used to indicate operations of the same names. Low is write.
- -- /NMI and /IRQ are the two interrupt pins. See the 6502 manual for more detailed explanation.
- -- M2 can be considered as a "signals ready" pin. It is actually a delayed form of CLK.
[edit] Status Flag Behavior
The status register doesn't implement bits 4 and 5. The only way to test those bits would be to push the status on the stack, but any time the status is pushed on the stack, those bits are set to fixed values, as described below.
When an IRQ or NMI occurs, the current status with bit 4 clear and bit 5 set is pushed on the stack, then the I flag is set.
PHP and BRK push the current status with bits 4 and 5 set on the stack; BRK then sets the I flag.
RTI and PLP set the status to the byte popped off the stack.
[edit] CPU Memory Map
| Addr | Size | Device |
|---|---|---|
| $0000 | $0800 | 2KB internal RAM |
| $0800 | $0800 | Mirrors of $0000-$07FF |
| $1000 | $0800 | |
| $1800 | $0800 | |
| $2000 | $0008 | NES PPU registers |
| $2008 | $1FF8 | Mirrors of $2000 every 8 bytes |
| $4000 | $0018 | NES APU and I/O registers |
| $4018 | $FFFF | Cartridge PRG ROM, cartridge PRG RAM, and mapper registers |
$FFFA - NMI vector
$FFFC - Reset vector
$FFFE - IRQ/BRK vector
[edit] Undocumented Instructions
Kevtris has confirmed that all illegal 6502 opcodes execute identically on the 2A03/2A07. He has even went as far as to integrate them into the CopyNES BIOS.
