PRG RAM circuit

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The iNES format implies 8 KiB of PRG RAM at $6000-$7FFF, which may or may not be battery backed, even for discrete boards such as NROM and UxROM that never actually had SRAM there.

Contents 1 kyuusaku's circuit 2 Bregalad's circuit 3 kyuusaku's second circuit 4 More suggestions from kyuusaku

[edit] kyuusaku's circuit

On the forum, kyuusaku has suggested an SRAM decoder circuit[1] to approximate this behavior in an NES cartridge board. It can be built from 7400 series parts: a 74HC00 (4 NANDs) and a 74HC04 (6 inverters), or from two 74HC00s (because a NAND with both inputs equal acts as an inverter).

NES cart edge                     SRAM chip
                       ___
R/W ----+-------------|   `.
        |             |     )o--------- /OE
Phi2 ---(----------+--|___,'
        |          |
        |          |   ___
        |          `--|   `.
        |  |`.        |     )o--------- /WE
        `--|  >o------|___,'
           |,'

           ___
/ROMSEL --|   `.    |`.       ___
          |     )o--|  >o----|   `.
A14 ------|___,'    |,'      |     )o-- /CE
                          ,--|___,'
A13 ---------------------'

kyuusaku also pointed out that a 74HC138 or 74HC139 can decode the address using one spare inverter, leaving the details as an exercise for the reader.

[edit] Bregalad's circuit

Bregalad suggested an even simpler circuit using one 74HC08, 74HC20, or 74HC21 chip, which exploits the 6264 SRAM's /WE behavior:[2]

AND A13, A14, /ROMSEL and PHI2 together (it shouldn't matter in which order) and feed the output to positive chip enable pin, ground the negative chip enable pin and connect /WE to R/W and /OE to ground and that should to it.

One side of a 74HC21 (dual 4-input AND) or 74HC20 (dual 4-input NAND) could compute the same function.

[edit] kyuusaku's second circuit

kyuusaku found potential timing problems with Bregalad's circuit and suggested a refinement of his own circuit based on a 7410 (triple 3-input NAND):[3]

NES cart edge                  RAM

              ____
/ROMSEL -----|    `-.
             |       \
A14 ---------|        )o------ /CS
             |       /
A13 ---------|____,-'

              ____
R/W ---------|    `-.
             |       \
Phi2 -----+--|        )o--+--- /OE
          |  |       /    |
          +--|____,-'     |
          |               |
          |   ____        |
          +--|    `-.     |
          |  |       \    |
          +--|        )o--(--- /WE
             |       /    |
          ,--|____,-'     |
          |               |
          `---------------'

On each of the NANDs that produce /OE and /WE, one Phi2 input can be replaced with Vdd (constant +5 V) if it simplifies routing.

[edit] More suggestions from kyuusaku

kyuusaku found "a race condition that could trigger unintentional writes" in the second circuit. Then he figured how to stick a pulldown on CE2 to take advantage of Phi2 going high-impedance during reset in order to "offer some write protection".[4]

           ,-------------- ROM /CE
          |   ____
/ROMSEL --+--|    `-.
             |       \
A14 ---------|        )o-- RAM /CE
             |       /
A13 ---------|____,-'

              ____
+5V ------+--|    `-.
          |  |       \
          `--|        )o-- ROM /OE
             |       /
R/W ------+--|____,-'
          |
          `--------------- RAM /WE

Phi2 ---------+----------- RAM CE2
              |
              <
              < "big R"
              <
              |
GND ----------+----------- RAM /OE

He also suggested a circuit based on a 74HC20 (double 4-input NAND):

Or you could just use a NAND4 to decode any active low memory, also using the /WE priority method. If this is done with a two gate 7420, the second gate could be used to invert r/w to prevent bus conflicts as in the circuit above. This is probably the *final* best way unless you happen to need the extra AND3 from the 7410 and have a positive CE.